Read interleaving

AXI4 read interleaving allows multiple read transactions from different IDs to be interleaved on the same read data channel (R channel). This is useful in high-performance systems where multiple masters or outstanding transactions need to share bandwidth efficiently.

Example Scenario of AXI4 Read Interleaving

System Setup:

  • A master initiates read transactions to different memory locations.
  • The slave supports interleaved read responses, meaning it can return data out of order as long as RID (Read ID) is used to identify responses correctly.
  • The interleaving is controlled using the ARQOS (read QoS) and RREADY signals.

Read Transaction Details:

ID Address Burst Type Data Count
1 0x1000 INCR 4
2 0x2000 INCR 4
  1. The master sends two read transactions with different IDs (RID 1 and RID 2).
  2. The slave starts responding to ID 1 first but then interleaves responses from ID 2.
  3. The responses on the R channel are interleaved but correctly marked with RID.

Example of Read Interleaving Sequence:

Cycle RVALID RID RDATA RLAST
1 1 1 Data1_0 0
2 1 2 Data2_0 0
3 1 1 Data1_1 0
4 1 2 Data2_1 0
5 1 1 Data1_2 0
6 1 2 Data2_2 0
7 1 1 Data1_3 1
8 1 2 Data2_3 1

Key Takeaways:

  • Each response is marked with RID so the master can reorder them correctly.
  • The order of responses is interleaved, meaning one burst doesn't need to complete before another can start.
  • RLAST is used to indicate the last transfer of each burst.

Would you like a Verilog/SystemVerilog simulation snippet for this?

 

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